"A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel ..."

Junichi Miyakoshi et al. (2006)

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DOI: 10.1109/VLSISOC.2006.313232

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-11

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Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno:
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. VLSI-SoC 2006: 192-197

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