"Logic synthesis and verification on fixed topology."

Masahiro Fujita, Alan Mishchenko (2014)

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DOI: 10.1109/VLSI-SOC.2014.7004155

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Masahiro Fujita, Alan Mishchenko:
Logic synthesis and verification on fixed topology. VLSI-SoC 2014: 1-6

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