"A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse ..."

Grégoire Eggermann et al. (2023)

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DOI: 10.1109/VLSI-SOC57769.2023.10321838

access: closed

type: Conference or Workshop Paper

metadata version: 2023-12-06

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Grégoire Eggermann, Marco Rios, Giovanni Ansaloni, Sani R. Nassif, David Atienza:
A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication. VLSI-SoC 2023: 1-6

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