"Power-aware test optimization for core-based 3D-SOCs under TSV-constraints."

Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya (2016)

> Home

Details and statistics

DOI: 10.1109/VLSI-SOC.2016.7753537

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsi/BanerjeeMB16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi/BanerjeeMB16
Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya:
Power-aware test optimization for core-based 3D-SOCs under TSV-constraints. VLSI-SoC 2016: 1-6

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.