"Timing-aware clock gating of pulsed-latch circuits for low power design."

Zong-Han Yang, Tsung-Yi Ho (2013)

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DOI: 10.1109/VLDI-DAT.2013.6533819

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-25

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Zong-Han Yang, Tsung-Yi Ho:
Timing-aware clock gating of pulsed-latch circuits for low power design. VLSI-DAT 2013: 1-4

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