"Layout placement optimization with isolation rings for high-voltage VLSI ..."

Chih-Wei Lee et al. (2017)

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DOI: 10.1109/VLSI-DAT.2017.7939658

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-20

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Chih-Wei Lee, Hwa-Yi Tseng, Chi-Lien Kuo, Chien-Nan Jimmy Liu, Chin Hsia:
Layout placement optimization with isolation rings for high-voltage VLSI circuits. VLSI-DAT 2017: 1-4

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