"Current source model of combinational logic gates for accurate gate-level ..."

Kai Chen, Young Hwan Kim (2015)

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DOI: 10.1109/VLSI-DAT.2015.7114529

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Kai Chen, Young Hwan Kim:
Current source model of combinational logic gates for accurate gate-level circuit analysis and timing analysis. VLSI-DAT 2015: 1-4

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