"Low-power gated clock tree optimization for three-dimensional integrated ..."

Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin (2015)

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DOI: 10.1109/VLSI-DAT.2015.7114530

access: closed

type: Conference or Workshop Paper

metadata version: 2023-11-12

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Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin:
Low-power gated clock tree optimization for three-dimensional integrated circuits. VLSI-DAT 2015: 1-4

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