"FPGA based hardware architectures for iterative algorithms implementations."

Bogdan Belean, Monica Borda, Adrian Bot (2013)

> Home

Details and statistics

DOI: 10.1109/TSP.2013.6614038

access: closed

type: Conference or Workshop Paper

metadata version: 2019-10-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/tsp/BeleanBB13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/tsp/BeleanBB13
Bogdan Belean, Monica Borda, Adrian Bot:
FPGA based hardware architectures for iterative algorithms implementations. TSP 2013: 751-754

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.