"A 0.5V Low-Power All-Digital Phase-Locked Loop in 65nm CMOS Process for ..."

Fredrick Angelo R. Galapon et al. (2018)

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DOI: 10.1109/TENCON.2018.8650488

access: closed

type: Conference or Workshop Paper

metadata version: 2019-07-30

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Fredrick Angelo R. Galapon, Mark Allen D. C. Agaton, Arcel G. Leynes, Lemuel Neil M. Noveno, Anastacia B. Alvarez, Chris Vincent J. Densing, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon, Rico Jossel M. Maestro:
A 0.5V Low-Power All-Digital Phase-Locked Loop in 65nm CMOS Process for Wireless Sensing Applications. TENCON 2018: 2122-2126

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