"VLSI layout and packaging of butterfly networks."

Chi-Hsiang Yeh et al. (2000)

> Home

Details and statistics

DOI: 10.1145/341800.341823

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/spaa/YehPVL00
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/spaa/YehPVL00
Chi-Hsiang Yeh, Behrooz Parhami, Emmanouel A. Varvarigos, Hua Lee:
VLSI layout and packaging of butterfly networks. SPAA 2000: 196-205

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.