"Stacking memory architecture exploration for three-dimensional integrated ..."

Hsien-Ching Hsieh et al. (2012)

> Home

Details and statistics

DOI: 10.1109/SOCC.2012.6398334

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/socc/HsiehHLL12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/socc/HsiehHLL12
Hsien-Ching Hsieh, Po-Han Huang, Chi-Hung Lin, Huang-Lun Lin:
Stacking memory architecture exploration for three-dimensional integrated circuit in 3-D PAC. SoCC 2012: 317-321

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.