"Formal Verification of Nonlinear Analog Circuits using State Space-Based ..."

Yasmine Abu-Haeyeh, Lars Hedrich (2024)

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DOI: 10.1109/SMACD61181.2024.10745444

access: closed

type: Conference or Workshop Paper

metadata version: 2024-12-02

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Yasmine Abu-Haeyeh, Lars Hedrich:
Formal Verification of Nonlinear Analog Circuits using State Space-Based Model Order Reduction. SMACD 2024: 1-4

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