"High-Speed Pipelined EGG Processor on FPGA."

William N. Chelton, Mohammed Benaissa (2006)

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DOI: 10.1109/SIPS.2006.352569

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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William N. Chelton, Mohammed Benaissa:
High-Speed Pipelined EGG Processor on FPGA. SiPS 2006: 136-141

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