"Transistor-Level Logic Gates Ranking Strategy for Selective Hardening."

Glória D. Claro da Silva, Rafael B. Schvittz, Paulo F. Butzen (2024)

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DOI: 10.1109/SBESC65055.2024.10771816

access: closed

type: Conference or Workshop Paper

metadata version: 2024-12-18

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Glória D. Claro da Silva, Rafael B. Schvittz, Paulo F. Butzen:
Transistor-Level Logic Gates Ranking Strategy for Selective Hardening. SBESC 2024: 1-6

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