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"Design and implementation of a modular, low latency, fault-aware, ..."

Roberto Ammendola et al. (2013)

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DOI: 10.1109/RECONFIG.2013.6732275

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-15

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  - conf/reconfig/AmmendolaBFCLPRSTV13
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  - https://dblp.org/rec/conf/reconfig/AmmendolaBFCLPRSTV13
Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini:
Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface. ReConFig 2013: 1-6

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