"A technique for power reduction of CMOS circuit at 65nm technology."

Angshuman Chakraborty, Sambhu Nath Pradhan (2012)

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DOI: 10.1109/RAIT.2012.6194592

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

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Angshuman Chakraborty, Sambhu Nath Pradhan:
A technique for power reduction of CMOS circuit at 65nm technology. RAIT 2012: 576-580

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