"500 MHz CMOS 28-nm Floating Point Arithmetic Unit for 32-Bit RISC-V ..."

Mattia Tambaro et al. (2024)

> Home

Details and statistics

DOI: 10.1109/PRIME61930.2024.10559675

access: closed

type: Conference or Workshop Paper

metadata version: 2024-07-04

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/prime/TambaroCGGMM24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/prime/TambaroCGGMM24
Mattia Tambaro, Silvia Ceopi, Andrea Gallacci, Andrea La Gala, Mirco Malanchini, Marcello De Matteis:
500 MHz CMOS 28-nm Floating Point Arithmetic Unit for 32-Bit RISC-V Microprocessors. PRIME 2024: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.