"Logic-Level Fast Current Simulation for Digital CMOS Circuits."

Paulino Ruiz-de-Clavijo et al. (2005)

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DOI: 10.1007/11556930_44

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-21

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Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo:
Logic-Level Fast Current Simulation for Digital CMOS Circuits. PATMOS 2005: 425-435

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