"Accurate error bit mode analysis of STT-MRAM chip with a novel current ..."

Ryo Tamura et al. (2018)

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DOI: 10.1109/NVMTS.2018.8603113

access: closed

type: Conference or Workshop Paper

metadata version: 2020-12-04

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  - conf/nvmts/TamuraMWKE18
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  - https://dblp.org/rec/conf/nvmts/TamuraMWKE18
Ryo Tamura, I. Mori, N. Watanabe, Hiroki Koike, Tetsuo Endoh:
Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system. NVMTS 2018: 1-5

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