"Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process."

Fredrick Angelo R. Galapon et al. (2018)

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DOI: 10.1109/NGCAS.2018.8572265

access: closed

type: Conference or Workshop Paper

metadata version: 2018-12-20

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Fredrick Angelo R. Galapon, Mark Allen D. C. Agaton, Arcel G. Leynes, Lemuel Neil M. Noveno, Anastacia B. Alvarez, Chris Vincent J. Densing, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon, Rico Jossel M. Maestro:
Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process. NGCAS 2018: 70-73

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