"Power-Silicon Efficient All-Digital △Σ TDC with Differential ..."

Parth Parekh, Fei Yuan (2018)

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DOI: 10.1109/NEWCAS.2018.8585621

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-15

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Parth Parekh, Fei Yuan:
Power-Silicon Efficient All-Digital △Σ TDC with Differential Gated Delay Line Time Integrator. NEWCAS 2018: 191-194

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