"Low temperature multi-layer wafer level package for chip scale atomic ..."

Nannan Li et al. (2015)

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DOI: 10.1109/NEMS.2015.7147472

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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Nannan Li, Yangxi Zhang, Ningli Zhu, Yunhui Zhu, Chengchen Gao, Jing Chen:
Low temperature multi-layer wafer level package for chip scale atomic clock (CSAC). NEMS 2015: 481-484

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