"High Performance Multiplierless Serial Pipelined VLSI Architecture for ..."

Jinti Hazarika et al. (2019)

> Home

Details and statistics

DOI: 10.1109/NCC.2019.8732236

access: closed

type: Conference or Workshop Paper

metadata version: 2019-10-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ncc/HazarikaKAN19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ncc/HazarikaKAN19
Jinti Hazarika, Mohd. Tasleem Khan, Shaik Rafi Ahamed, Harshal B. Nemade:
High Performance Multiplierless Serial Pipelined VLSI Architecture for Real-Valued FFT. NCC 2019: 1-6

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.