"An 8b 5-GS/s CMOS SAR ADC with speed optimized SAR logic."

Aarti Shah, Bibhu Datta (2017)

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DOI: 10.1109/MWSCAS.2017.8053210

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-25

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Aarti Shah, Bibhu Datta:
An 8b 5-GS/s CMOS SAR ADC with speed optimized SAR logic. MWSCAS 2017: 1465-1468

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