"A highly linear 4-bit DAC with 1 GHz sampling rate implemented in 28 nm ..."

Zbigniew Jaworski (2017)

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DOI: 10.23919/MIXDES.2017.8005181

access: closed

type: Conference or Workshop Paper

metadata version: 2017-09-16

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Zbigniew Jaworski:
A highly linear 4-bit DAC with 1 GHz sampling rate implemented in 28 nm FD-SOI process. MIXDES 2017: 189-195

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