"Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power ..."

Henrique Kessler et al. (2022)

> Home

Details and statistics

DOI: 10.1109/LASCAS53948.2022.9789079

access: closed

type: Conference or Workshop Paper

metadata version: 2023-06-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/lascas/KesslerBRPC22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/lascas/KesslerBRPC22
Henrique Kessler, Murilo Bohlke, Leomar S. da Rosa, Marcelo Schiavon Porto, Vinicius V. Camargo:
Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design. LASCAS 2022: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.