"A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture."

Syed Masood Ali, Rabin Raut, Mohamad Sawan (2005)

Details and statistics

DOI: 10.1109/IWSOC.2005.22

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.