"An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem."

Zarrin Tasnim Sworna et al. (2017)

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DOI: 10.1109/ISVLSI.2017.29

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/isvlsi/SwornaHBJB17
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal, Ashis Kumer Biswas:
An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem. ISVLSI 2017: 116-121

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