"Validating Delay Bounds in Networks on Chip: Tightness and Pitfalls."

Alberto Saggio et al. (2015)

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DOI: 10.1109/ISVLSI.2015.111

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Alberto Saggio, Gaoming Du, Xueqian Zhao, Zhonghai Lu:
Validating Delay Bounds in Networks on Chip: Tightness and Pitfalls. ISVLSI 2015: 404-409

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