"Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined ..."

Xi Li et al. (2022)

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DOI: 10.1109/ISVLSI54635.2022.00024

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type: Conference or Workshop Paper

metadata version: 2024-05-07

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Xi Li, Min Pan, Tong Liu, Peter A. Beerel:
Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic. ISVLSI 2022: 62-67

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