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"A Low Power, High Performance Threshold Logic-Based Standard Cell ..."
Samuel Leshner et al. (2010)
- Samuel Leshner, Krzysztof S. Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma B. K. Vrudhula:
A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. ISVLSI 2010: 210-215
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