"Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology."

Hung-Chang Yu et al. (2013)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2013.6487710

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/YuLLHCOCNT13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/YuLLHCOCNT13
Hung-Chang Yu, Kai-Chun Lin, Ku-Feng Lin, Chin-Yi Huang, Yu-Der Chih, Tong-Chern Ong, Tsung-Yung Jonathan Chang, Sreedhar Natarajan, Luan C. Tran:
Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology. ISSCC 2013: 224-225

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.