"An 80MHz-BW 31.9fJ/conv-step Filtering ΔΣ ADC with a Built-In ..."

Chi-Yun Wang et al. (2019)

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DOI: 10.1109/ISSCC.2019.8662416

access: closed

type: Conference or Workshop Paper

metadata version: 2019-03-12

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Chi-Yun Wang, Jen-Huan Tsai, Sheng-Yuan Su, Jen-Che Tsai, Jhy-Rong Chen, Chih-Hong Lou:
An 80MHz-BW 31.9fJ/conv-step Filtering ΔΣ ADC with a Built-In DAC-Segmentation/ELD-Compensation 6b 960MS/s SAR-Quantizer in 28nm LP for 802.11ax Applications. ISSCC 2019: 338-340

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