"A 72Mb Separate-I/O Synchronous SRAM Chip with 504Gb/s Data Bandwidth."

Chih Tseng et al. (2006)

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DOI: 10.1109/ISSCC.2006.1696324

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-14

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Chih Tseng, Jae-Hyeong Kim, Suzanne Chen, Mu-Hsiang Huang, Chungji Lu, Ikio Hashiguchi, Yoshifumi Miyazima, Masahiro Ichihashi, Kentaro Maki, Katsuya Nakashima, Patrick Chuang:
A 72Mb Separate-I/O Synchronous SRAM Chip with 504Gb/s Data Bandwidth. ISSCC 2006: 2582-2591

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