default search action
"A 43.7mW 96GHz PLL in 65nm CMOS."
Kun-Hung Tsai, Shen-Iuan Liu (2009)
- Kun-Hung Tsai, Shen-Iuan Liu:
A 43.7mW 96GHz PLL in 65nm CMOS. ISSCC 2009: 276-277
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.