"A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in ..."

Yasuhide Shimizu et al. (2008)

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DOI: 10.1109/ISSCC.2008.4523302

access: closed

type: Conference or Workshop Paper

metadata version: 2020-08-13

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Yasuhide Shimizu, Shigemitsu Murayama, Kohhei Kudoh, Hiroaki Yatsuda:
A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOS. ISSCC 2008: 552-553

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