"17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms ..."

Pratap Tumkur Renukaswamy et al. (2020)

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DOI: 10.1109/ISSCC19947.2020.9063080

access: closed

type: Conference or Workshop Paper

metadata version: 2022-12-07

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Pratap Tumkur Renukaswamy, Nereo Markulic, Sehoon Park, Anirudh Kankuppe, Qixian Shi, Piet Wambacq, Jan Craninckx:
17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth. ISSCC 2020: 278-280

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