"A 40GOPS 250mW massively parallel processor based on matrix architecture."

Masami Nakajima et al. (2006)

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DOI: 10.1109/ISSCC.2006.1696216

access: closed

type: Conference or Workshop Paper

metadata version: 2020-06-09

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Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu:
A 40GOPS 250mW massively parallel processor based on matrix architecture. ISSCC 2006: 1616-1625

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