"A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOS Using a Tri-State ..."

Takashi Masuda et al. (2007)

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DOI: 10.1109/ISSCC.2007.373482

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Takashi Masuda, Hideyuki Suzuki, Hiroshi Iizuka, Akio Igarashi, Kaneyoshi Takeshita, Takayuki Mogi, Takayuki Shoji, Jeremy Chatwin, Iain Butler, Derek Mellor:
A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOS Using a Tri-State Binary PD with 100ps Gated Digital Output. ISSCC 2007: 438-614

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