"A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with ..."

Wenbo Liu et al. (2009)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2009.4977318

access: closed

type: Conference or Workshop Paper

metadata version: 2021-03-09

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/LiuCHCLCYMC09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/LiuCHCLCYMC09
Wenbo Liu, Yuchun Chang, Szukang Hsien, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu:
A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization. ISSCC 2009: 82-83

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.