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"15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with ..."
Martin Kramer et al. (2015)
- Martin Kramer, Erwin Janssen, Kostas Doris, Boris Murmann:
15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS. ISSCC 2015: 1-3
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