"17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing ..."

John Keane et al. (2016)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2016.7418030

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/KeaneKKNGKZ16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/KeaneKKNGKZ16
John Keane, Jaydeep Kulkarni, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang:
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology. ISSCC 2016: 308-309

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.