"A fractional-N digital PLL with background-dither-noise-cancellation loop ..."

Cheng-Ru Ho, Mike Shuo-Wei Chen (2018)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2018.8310350

access: closed

type: Conference or Workshop Paper

metadata version: 2018-03-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/HoC18a
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/HoC18a
Cheng-Ru Ho, Mike Shuo-Wei Chen:
A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS. ISSCC 2018: 394-396

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.