"A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory."

Yuriy M. Greshishchev et al. (2011)

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DOI: 10.1109/ISSCC.2011.5746279

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Yuriy M. Greshishchev, Daniel Pollex, Shing-Chi Wang, Marinette Besson, Philip Flemeke, Stefan Szilagyi, Jorge Aguirre, Chris Falt, Naim Ben-Hamida, Robert Gibbins, Peter Schvan:
A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory. ISSCC 2011: 194-196

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