"An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS."

Vito Giannini et al. (2008)

Details and statistics

DOI: 10.1109/ISSCC.2008.4523145

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

a service of  Schloss Dagstuhl - Leibniz Center for Informatics