"A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC."

Siddharth Devarajan et al. (2009)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2009.4977320

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/DevarajanSKDKW09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/DevarajanSKDKW09
Siddharth Devarajan, Larry Singer, Dan Kelly, Steven Decker, Abhishek Kamath, Paul Wilkins:
A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC. ISSCC 2009: 86-87

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.