"A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in ..."

Jan Craninckx, Geert Van der Plas (2007)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2007.373386

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/CraninckxP07
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/CraninckxP07
Jan Craninckx, Geert Van der Plas:
A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS. ISSCC 2007: 246-600

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.