"A 256kb Sub-threshold SRAM in 65nm CMOS."

Benton H. Calhoun, Anantha P. Chandrakasan (2006)

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DOI: 10.1109/ISSCC.2006.1696325

access: closed

type: Conference or Workshop Paper

metadata version: 2021-09-27

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Benton H. Calhoun, Anantha P. Chandrakasan:
A 256kb Sub-threshold SRAM in 65nm CMOS. ISSCC 2006: 2592-2601

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