"A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13µm CMOS."

Peter Bogner et al. (2006)

Details and statistics

DOI: 10.1109/ISSCC.2006.1696123

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-14

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.